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ltc4228-1/ltc4228-2 1 422812f cpo1 on1 137k 12v 12v on2 intv cc gnd 0.1f 0.1f 0.1f 47nf 47nf in1 sense1 ? sense1 + dgate1 si7336adp ltc4228 0.004 si7336adp si7336adp 0.004 si7336adp hgate1 out1 cpo2 in2 sense2 ? sense2 + dgate2 hgate2 out2 status1 fault1 pwrgd1 en1 en2 pwrgd2 fault2 status2 20k 20k 137k 12v 7.6a plug-in card 1 plug-in card 2 backplane 422812 ta01a 12v 7.6a tmr1 tmr2 i in2 2a/div i in1 2a/div in2 1v/div in1 1v/div 200ms/div 422512 ta01b typical a pplica t ion fea t ures descrip t ion dual ideal diode and hot swap controller the ltc ? 4228 offers ideal diode and hot swap? functions for two power rails by controlling two external n-channel mosfets in each rail. mosfets acting as ideal diodes re - place two high power schottky diodes and the associated heat sinks, saving power and board area. hot swap control mosfets allow boards to be safely inserted and removed from a live backplane by limiting inrush current. the supply output is also protected against short-circuit faults with a fast acting current limit and internal timed circuit breaker. the ltc4228 regulates the forward voltage drop across the external mosfets and sense resistor to ensure smooth current transfer from one supply to the other without oscillation. the ideal diodes turn on quickly to reduce the load voltage droop during supply switch-over. if the input supply fails or is shorted, a fast turn-off minimizes reverse-current transients. the ltc4228 allows independent on/off control, and reports fault and power good status for the supply. the ltc4228 improves on the ltc4225 by recovering more quickly from input brownouts to preserve the output voltage. tca application a pplica t ions n power path and inrush current control for redundant supplies n low loss replacement for power schottky diodes n protects output voltage from input brownouts n allows safe hot swapping from a live backplane n 2.9v to 18v operating range n controls n-channel mosfets n limits peak fault current in 1s n adjustable current limit with circuit breaker n adjustable current limit fault delay n smooth switchover without oscillation n 0.5s ideal diode turn-on and t urn-off time n status, fault and power good outputs n ltc4228-1: latch off after fault n ltc4228-2: automatic retry after fault n 28-lead 4mm 5mm qfn and ssop packages n redundant power supplies n microtca systems and servers n telecom networks n power prioritizer l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. hot swap is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. smooth supply switchover
ltc4228-1/ltc4228-2 2 422812f a bsolu t e maxi m u m r a t ings supply voltages in1 , in2 .................................................. C 0.3v to 24v in tv cc ..................................................... C0 .3v to 7v input voltages on1 , on2, en1 , en2 ............................... C0.3v to 24v tmr 1, tmr2 ......................... C 0.3v to intv cc + 0.3v se nse1 + , sense2 + ................................ C0 .3v to 24v se nse1 C , sense2 C ................................ C0.3v to 24v output voltages fa u lt1 , fa u lt2 , pwrgd1 , pwrgd2 ..... C 0.3v to 24v stat us1 , status2 ................................ C 0.3v to 24v cp o1, cpo2 (note 3) ............................. C 0.3v to 35v dga te1, dgate2 (note 3) ..................... C 0.3v to 35v (notes 1, 2) 9 10 top view ufd package 28-lead (4mm 5mm) plastic qfn 11 12 13 28 29 27 26 25 24 14 23 6 5 4 3 2 1 sense1 ? sense1 + in1 intv cc gnd in2 sense2 + sense2 ? fault1 on1 en1 tmr1 tmr2 en2 on2 fault2 dgate1 cpo1 status1 hgate1 out1 pwrgd1 dgate2 cpo2 status2 hgate2 out2 pwrgd2 7 17 18 19 20 21 22 16 8 15 t jmax = 125c, ja = 43c/w (note 5) exposed pad (pin 29) pcb gnd connection optional 1 2 3 4 5 6 7 8 9 10 11 12 13 14 top view gn package 28-lead plastic ssop narrow 28 27 26 25 24 23 22 21 20 19 18 17 16 15 status1 cpo1 dgate1 sense1 ? sense1 + in1 intv cc gnd in2 sense2 + sense2 ? dgate2 cpo2 status2 hgate1 out1 pwrgd1 fault1 on1 en1 tmr1 tmr2 en2 on2 fault2 pwrgd2 out2 hgate2 t jmax = 125c, ja = 80c/w p in c on f igura t ion hgate1, hgate2 (note 4) ..................... C 0.3v to 35v out 1, out2 ........................................... C0 .3v to 24v average currents fa u lt1 , fa u lt2 , pwrgd1 , pwrgd2 ................... 5m a stat us1 , status2 .............................................. 5m a in tv cc ................................................................. 1ma o perating temperature range lt c4228c ................................................ 0 c to 70c lt c4228i ............................................. C4 0c to 85c storage temperature range .................. C 65c to 150c lead temperature (soldering, 10 sec) gn p ackage ...................................................... 3 00c
ltc4228-1/ltc4228-2 3 422812f o r d er i n f or m a t ion lead free finish tape and reel part marking* package description temperature range ltc4228cufd-1#pbf ltc4228cufd-1#trpbf 42281 28-lead (4mm 5mm) plastic qfn 0c to 70c ltc4228cufd-2#pbf ltc4228cufd-2#trpbf 42282 28-lead (4mm 5mm) plastic qfn 0c to 70c ltc4228iufd-1#pbf ltc4228iufd-1#trpbf 42281 28-lead (4mm 5mm) plastic qfn C40c to 85c ltc4228iufd-2#pbf ltc4228iufd-2#trpbf 42282 28-lead (4mm 5mm) plastic qfn C40c to 85c ltc4228cgn-1#pbf ltc4228cgn-1#trpbf ltc4228gn-1 28-lead plastic ssop 0c to 70c ltc4228cgn-2#pbf ltc4228cgn-2#trpbf ltc4228gn-2 28-lead plastic ssop 0c to 70c ltc4228ign-1#pbf ltc4228ign-1#trpbf ltc4228gn-1 28-lead plastic ssop C40c to 85c ltc4228ign-2#pbf ltc4228ign-2#trpbf ltc4228gn-2 28-lead plastic ssop C40c to 85c consult ltc marketing for parts specifed with wider operating temperature ranges. *the temperature grade is identifed by a label on the shipping container. consult ltc marketing for information on non-standard lead based fnish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifcations, go to: http://www.linear.com/tapeandreel/ e lec t rical c harac t eris t ics the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. v in = 12v, unless otherwise noted. symbol parameter conditions min typ max units supplies v in input supply range l 2.9 18 v i in input supply current l 2.5 5 ma v intvcc internal regulator voltage i = 0, C500a l 4.5 5 5.6 v v intvcc(uvl) internal v cc undervoltage lockout intv cc rising l 2.1 2.2 2.3 v ?v intvcc(hyst) internal v cc undervoltage lockout hysteresis l 30 60 90 mv ideal diode control ?v fwd(reg) forward regulation voltage (v inn C v outn ) l 10 25 40 mv ?v dgate external n-channel gate drive (v dgaten C v inn ) in < 7v, ?v fwd = 0.1v, i = 0, C1a in = 7v to 18v, ? v fwd = 0.1v, i = 0, C1a l l 5 10 7 12 14 14 v v ?v dgate(st) diode mosfet on detect threshold status pulls low, ?v fwd = 50mv l 0.3 0.7 1.1 v i cpo(up) cpon pull-up current cpo = in = 2.9v cpo = in = 18v l l C60 C50 C95 C85 C120 C110 a a i dgate(fpu) dgaten fast pull-up current ?v fwd = 0.2v, ?v dgate = 0v, cpo = 17v C1.5 a i dgate(fpd) dgaten fast pull-down current ?v fwd = C0.2v, ?v dgate = 5v 1.5 a t on(dgate) dgaten turn-on delay ?v fwd = 0.2v, c dgate = 10nf l 0.25 0.5 s t off(dgate) dgaten turn-off delay ?v fwd = C0.2v, c dgate = 10nf l 0.2 0.5 s hot swap control ?v sense(cb) circuit breaker trip sense voltage (v sensen + C v sensen C ) l 47.5 50 52.5 mv ?v sense(acl) active current limit sense voltage (v sensen + C v sensen C ) l 55 65 75 mv v sense + (uvl) sensen + undervoltage lockout sense + rising l 1.75 1.9 2.05 v ? v sense + (hyst) sensen + undervoltage lockout hysteresis l 10 50 90 mv i sense + sensen + input current sense + = 12v l 150 350 500 a i sense C sensen C input current sense C = 12v l 10 50 100 a ?v hgate external n-channel gate drive (v hgaten C v outn ) in < 7v, i = 0, C1a in = 7v to 18v, i = 0, C1a l l 4.8 10 7 12 14 14 v v
ltc4228-1/ltc4228-2 4 422812f e lec t rical c harac t eris t ics the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. v in = 12v, unless otherwise noted. symbol parameter conditions min typ max units ?v hgate(pg) gate-source voltage for power good l 3.6 4.2 4.8 v i hgate(up) external n-channel gate pull-up current gate drive on, hgate = 0v l C7 C10 C13 a i hgate(dn) external n-channel gate pull-down current gate drive off, out = 12v, hgate = out + 5v l 150 300 500 a i hgate(fpd) external n-channel gate fast pull-down current fast turn-off, out = 12v, hgate = out + 5v l 100 200 300 ma t phl(sense) sense voltage (sensen + C sensen C ) high to hgaten low ?v sense = 300mv, c hgate = 10nf l 0.5 1 s t off(hgate) en n high to hgaten low onn low to hgaten low sensen + low to hgaten low l l l 20 10 10 40 20 20 s s s t d(hgate) onn high, en n low to hgaten turn-on delay l 50 100 150 ms t p(hgate) onn to hgaten propagation delay on = step 0.8v to 2v l 10 20 s input/output pin v on(th) onn threshold voltage on rising l 1.21 1.235 1.26 v ?v on(hyst) onn hysteresis l 40 80 140 mv v on(reset) onn fault reset threshold voltage on falling l 0.55 0.6 0.63 v i on(leak) onn input leakage current on = 5v l 0 1 a v en(th) en n threshold voltage en rising l 1.185 1.235 1.284 v ?v en(hyst) enn hysteresis l 40 130 200 mv i en(up) enn pull-up current en = 1v l C7 C10 C13 a v tmr(th) tmrn threshold voltage tmr rising tmr falling l l 1.198 0.15 1.235 0.2 1.272 0.25 v v i tmr(up) tmrn pull-up current tmr = 1v, in fault mode l C75 C100 C125 a i tmr(dn) tmrn pull-down current tmr = 2v, no faults l 1.4 2 2.6 a i tmr(ratio) tmrn current ratio i tmr(dn) /i tmr(up) l 1.4 2 2.7 % i out outn current out = 11v, in = 12v, on = 2v out = 13v, in = 12v, on = 2v l l 50 2.5 120 5 a ma v ol output low voltage ( faultn, pwrgdn, statusn) i = 1ma l 0.15 0.4 v v oh output high voltage ( faultn, pwrgdn, statusn) i = C1a l intv cc C 1 intv cc C 0.5 v i oh input leakage current ( faultn, pwrgdn, statusn) v = 18v l 0 1 a i pu output pull-up current ( faultn, pwrgdn, statusn) v = 1.5v l C7 C10 C13 a t rst(on) onn low to faultn high l 20 40 s note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all currents into device pins are positive; all currents out of device pins are negative. all voltages are referenced to gnd unless otherwise specifed. note 3: an internal clamp limits the dgate and cpo pins to a minimum of 10v above and a diode below in. driving these pins to voltages beyond the clamp may damage the device. note 4: an internal clamp limits the hgate pin to a minimum of 10v above and a diode below out. driving this pin to voltages beyond the clamp may damage the device. note 5: thermal resistance is specifed when the exposed pad is soldered to a 3" 4.5", four layer, fr4 board.
ltc4228-1/ltc4228-2 5 422812f typical p er f or m ance c harac t eris t ics diode gate voltage vs current hot swap gate voltage vs current out current vs voltage circuit breaker trip voltage vs temperature active current limit sense voltage vs temperature active current limit delay vs sense voltage in supply current vs voltage intv cc load regulation cpo voltage vs current t a = 25c, v in = 12v, unless otherwise noted. i load (ma) 0 0 intv cc (v) 1 2 3 4 5 6 ?2 ?4 ?6 ?8 422812 g02 ?10 v in = 12v v in = 3.3v v out (v) 0 ?0.5 i out (ma) 0 0.5 1.0 1.5 2.0 3.0 3 6 9 12 422812 g06 15 18 2.5 v in = 12v temperature (c) ?50 48 circuit breaker trip voltage (mv) 49 50 51 52 ?25 0 25 50 422812 g07 75 100 temperature (c) ?50 63 active current limit sense voltage (mv) 64 65 66 67 ?25 0 25 50 422812 g08 75 100 sense voltage (v in ? v sense ) (mv) 50 0.1 active current limit delay (s) 10 100 100 150 200 250 300 422812 g09 1 c hgate = 10nf i hgate (a) 0 14 12 10 8 6 4 2 0 ?6 ?10 422812 g05 ?2 ?4 ?8 ?12 gate drive (?v hgate ) (v) v in = 12v v out = v in v in = 2.9v i dgate (a) 0 12 10 8 6 4 2 0 ?2 ?60 ?100 422812 g04 ?20 ?40 ?80 ?120 v dgate ? v in (?v dgate ) (v) v in = 18v v in = 2.9v v out = v in ? 0.1v v in (v) 0 0 i in (ma) 1 2 3 4 3 6 9 12 422812 g01 15 18 i cpo (a) 0 12 10 8 6 4 2 0 ?2 ?60 ?100 422812 g03 ?20 ?40 ?80 ?120 v cpo ? v in (?v cpo ) (v) v in = 18v v in = 2.9v
ltc4228-1/ltc4228-2 6 422812f hgate pull-up current vs temperature tmr pull-up current vs temperature pwrgd , fault, status output low voltage vs current typical p er f or m ance c harac t eris t ics t a = 25c, v in = 12v, unless otherwise noted. p in func t ions cpo1, cpo2: charge pump output. connect a capacitor from cpo1 or cpo2 to the corresponding in1 or in2 pin. the value of this capacitor is approximately 10 the gate capacitance (c iss ) of the external mosfet for ideal diode control. the charge stored on this capacitor is used to pull up the gate during a fast turn-on. leave this pin open if fast turn-on is not needed. dgate1, dgate2: ideal diode mosfet gate drive out- put. connect this pin to the gate of an external n-channel mosfet for ideal diode control. an internal clamp limits the gate voltage to 12v above and a diode voltage below in. during fast turn-on, a 1.5a pull-up charges dgate from cpo. during fast turn-off, a 1.5a pull-down discharges dgate to in. en1, en2: enable input. ground this pin to enable hot swap control. if this pin is pulled high, the mosfet is not allowed to turn on. a 10a current source pulls this pin up to a diode below intv cc . upon en going low when on is high, an internal timer provides a 100ms start-up delay for debounce, after which the fault is cleared. exposed pad (ufd package): the exposed pad may be left open or connected to device ground. fault1 , fault2 : fault status output. open-drain output that is normally pulled high by a 10a current source to a diode below intv cc . it may be pulled above intv cc using an external pull-up. it pulls low when the circuit breaker is tripped after an overcurrent fault timeout. leave open if unused. gnd: device ground. hgate1, hgate2: hot swap mosfet gate drive output. connect this pin to the gate of the external n-channel mosfet for hot swap control. an internal 10a current source charges the mosfet gate. an internal clamp limits the gate voltage to 12v above and a diode below out. during turn-off, a 300a pull-down discharges hgate to ground. during an output short or intv cc undervoltage lockout, a fast 200ma pull-down discharges hgate to out. in1, in2: positive supply input and ideal diodes mosfet gate drive return. the 5v intv cc supply is generated from in1, in2, out1 and out2 via an internal diode-or. the voltage sensed at this pin is used to control dgate for forward voltage regulation and reverse turn-off. the gate fast pull-down current returns through this pin when dgate is discharged. temperature (c) ?50 ?9.0 hgate pull-up current (a) ?9.5 ?10.0 ?10.5 ?11.0 ?25 0 25 50 422812 g10 75 100 temperature (c) ?50 ?97 tmr pull-up current (a) ?98 ?99 ?100 ?101 ?103 ?25 0 25 50 422812 g11 75 100 ?102 current (ma) 0 output low voltage (v) 0.4 0.6 4 422812 g12 0.2 0 1 2 3 5 0.8
ltc4228-1/ltc4228-2 7 422812f p in func t ions intv cc : internal 5v supply decoupling output. this pin must have a 0.1f or larger capacitor. an external load of less than 500a can be connected at this pin. on1, on2: on control input. a rising edge above 1.235v turns on the external hot swap mosfet and a falling edge below 1.155v turns it off. connect this pin to an external resistive divider from in or sense + to monitor the supply undervoltage condition. pulling the on pin below 0.6v resets the electronic circuit breaker. out1, out2: output voltage sense and hot swaps mos- fet gate drive return. connect this pin to the output side of the external mosfet. the voltage sensed at this pin is used to control dgate. the gate fast pull-down current returns through this pin when hgate is discharged. pwrgd1 , pwrgd2 : power status output. open-drain output that is normally pulled high by a 10a current source to a diode below intv cc . it may be pulled above intv cc using an external pull-up. it pulls low when the mosfet gate drive between hgate and out exceeds the gate-to-source voltage of 4.2v. leave open if unused. sense1 + , sense2 + : positive current sense input. connect this pin to the output of the external ideal diode mosfet and input of the current sense resistor. the voltage sensed at this pin is used for monitoring the current limit. this pin has an undervoltage lockout threshold of 1.9v that will turn off the hot swap mosfet. sense1 C , sense2 C : negative current sense input. con- nect this pin to the output of the current sense resistor. the current limit circuit controls hgate to limit the voltage between sense + and sense C to 65mv. a circuit breaker trips when the sense voltage exceeds 50mv for more than a fault flter delay confgured at the tmr pin. status1 , status2 : diode mosfet status output. open-drain output that is normally pulled high by a 10a current source to a diode below intv cc . it may be pulled above intv cc using an external pull-up. it pulls low when the mosfet gate drive between dgate and in exceeds the gate-to-source voltage of 0.7v. leave open if unused. tmr1, tmr2: timer capacitor terminal. connect a capaci- tor between this pin and ground to set a 12ms/f duration for current limit before the external hot swap mosfet is turned off. the duration of the off time is 617ms/f, resulting in a 2% duty cycle.
ltc4228-1/ltc4228-2 8 422812f b lock diagra m + ? + ? a1 + ? ga1 hgate1 in1 cpo1 dgate1 out1 on1 hgate2 in2 cpo2 dgate2 out2 65mv 50mv 65mv 50mv sense1 + sense1 ? ecb1 sense2 ? sense2 + 10a + ? + ? 25mv hgate1 on 1.235v 0.6v 1.235v 0.6v 10a intv cc 10a intv cc cp1 25mv 2.2v + ? 100a intv cc 12v intv cc 10a 100a + ? a2 + ? intv cc intv cc uv3 + ? + ? + ? charge pump 1 f = 2mhz gate driver 1 gate driver 2 charge pump 2 f = 2mhz 5v ldo ga2 + ? 100a intv cc 2a + ? sense1 + 1.9v uv1 + ? fault1 reset cp2 cp5 + ? 1.235v 0.2v cp7 + ? cp8 100a 2a 1.235v 0.2v cp9 cp10 + ? 1.235v card1 presence detect hgate2 on fault2 reset logic card2 presence detect + ? tmr1 *ufd package only en1 on2 cp6 cp3 cp4 tmr2 422812 bd en2 intv cc + ? + ? + ? + ? 1.235v + ? sense2 + 1.9v uv2 + ? + ? ecb2 10a intv cc 10a intv cc gnd status1 fault1 pwrgd1 exposed pad* status2 fault2 pwrgd2 intv cc intv cc 10a 10a 12v 12v 12v 10a intv cc intv cc 10a dgate2 in2 0.7v stat2 + ? + ? 4.2v pg2 + ? hgate2 + ? 0.7v dgate1 in1 stat1 + ? +? hgate1 pg1 4.2v + ? +?
ltc4228-1/ltc4228-2 9 422812f o pera t ion the ltc4228 functions as an ideal diode with inrush cur - rent limiting and overcurrent protection by controlling two external n-channel mosfets (m d and m h ) on a supply path. this allows boards to be safely inserted and removed in systems with a backplane powered by redundant sup- plies, such as tca applications. the ltc4228 has two separate ideal diode and hot swap controllers, each providing independent control for the two input supplies. when the ltc4228 is frst powered up, the gates of the external mosfets are held low, keeping them off. the gate drive amplifer (ga1, ga2) monitors the voltage between the in and out pins and drives the dgate pin. the amplifer quickly pulls up the dgate pin, turning on the mosfet for ideal diode control, when it senses a large forward voltage drop. the stored charge in an external capacitor connected between the cpo and in pins provides the charge needed to quickly turn on the ideal diode mosfet. an internal charge pump charges up this capacitor at device power-up. the dgate pin sources current from the cpo pin and sinks current into the in and gnd pins. when the dgate to in voltage exceeds 0.7v, the status pin pulls low to indicate that the ideal diode mosfet is turned on. pulling the on pin high and the en pin low initiates a 100ms debounce timing cycle. after this timing cycle, a 10a current source from the charge pump ramps up the hgate pin. when the hot swap mosfet turns on, the inrush current is limited at a level set by an external sense resistor (r s ) connected between the sense + and sense C pins. an active current limit amplifer (a1, a2) servos the gate of the mosfet to 65mv across the current sense resistor. inrush current can be further reduced, if desired, by adding a capacitor from hgate to gnd. when the mosfet s gate overdrive (hga te to out voltage) exceeds 4.2v, the pwrgd pin pulls low. when both of the mosfets are turned on, the gate drive amplifer controls dgate to servo the forward voltage drop (v in C v out ) across the sense resistor and the two mosfets to 25mv. if the load current causes more than 25mv of voltage drop, the dgate voltage rises to enhance the mosfet used for ideal diode control. for large output currents, the ideal diode mosfet is driven fully on and the voltage drop across the mosfets is equal to the sum of the i load ? r ds(on) of the two mosfets in series. in the case of an input supply short circuit when the mosfets are conducting, a large reverse current starts fowing from the load towards the input. the gate drive amplifer detects this failure condition as soon as it ap- pears and turns off the ideal diode mosfet by pulling down the dgate pin. in the case where an overcurrent fault occurs on the sup - ply output, the current is limited to 65mv/r s . after a fault flter delay set by 100a charging the tmr pin capacitor, the circuit breaker trips and pulls the hgate pin low, turn - ing off the hot swap mosfet. only the supply at fault is affected, with the corresponding fault pin latched low. at this point, the dgate pin continues to pull high and keeps the ideal diode mosfet on. internal clamps limit both the dgate to in and cpo to in voltages to 12v. the same clamp also limits the cpo and dgate pins to a diode voltage below the in pin. another internal clamp limits the hgate to out voltage to 12v and also clamps the hgate pin to a diode voltage below the out pin. power to the ltc4228 is supplied from either the in or out pins, through an internal diode-or circuit to a low dropout regulator (ldo). that ldo generates a 5v supply at the intv cc pin and powers the ltc4228s internal low voltage circuitry.
ltc4228-1/ltc4228-2 10 422812f a pplica t ions i n f or m a t ion high availability systems often employ parallel-connected power supplies or battery feeds to achieve redundancy and enhance system reliability. power oring diodes are commonly used to connect these supplies at the point of load, but at the expense of power loss due to signifcant diode forward voltage drop. the ltc4228 minimizes this power loss by using external n-channel mosfets for the pass elements, allowing for a low voltage drop from the supply to the load when the mosfets are turned on. when an input source voltage drops below the output common supply voltage, the appropriate mosfet is turned off, thereby matching the function and performance of an ideal diode. by adding a current sense resistor in between the two external mosfets that are separately controlled, the ltc4228 enhances the ideal diode performance with inrush current limiting and overcurrent protection (see figure 1). this allows the boards to be safely inserted and removed from a live backplane without damaging the connector. internal v cc supply the ltc4228 can operate with input supplies from 2.9v to 18v at the in pins. the power supply to the device is internally regulated at 5v by a low dropout regulator (ldo) with an output at the intv cc pin. an internal diode-or circuit selects the highest of the supplies at the in and out pins to power the device through the ldo. the diode-or scheme permits the devices power to be temporarily kept alive by the out load capacitance when the in supplies have collapsed or shut off. an undervoltage lockout circuit prevents all of the mosfets from turning on until the intv cc voltage exceeds 2.2v. a 0.1f capacitor is recommended between the intv cc and gnd pins, close to the device for bypassing. no external supply should be connected at the intv cc pin so as not to affect the ldos operation. a small external load of less than 500a can be connected at the intv cc pin. turn-on sequence the board power supply at the out pin is controlled with two external n-channel mosfets (m d , m h ). the mosfet m d on the supply side functions as an ideal diode, while m h on the load side acts as a hot swap controlling the power supplied to the output load. the sense resistor, r s , figure 1. tca application supplying 12v power to two tca slots cpo1 on1 r2 137k r4 137k v in2 12v v in1 12v on2 intv cc gnd c1 0.1f c f1 10nf c f2 10nf c cp1 0.1f c cp2 0.1f c t2 47nf c hg1 15nf bulk supply bypass capacitor bulk supply bypass capacitor c t1 47nf 12v 7.6a plug-in card 1 plug-in card 2 backplane 422812 f01 in1 sense1 ? sense1 + dgate1 m d1 si7336adp m h1 si7336adp ltc4228 r s1 0.004 m d2 si7336adp m h2 si7336adp r s2 0.004 hgate1 out1 cpo2 in2 sense2 ? sense2 + dgate2 hgate2 out2 status1 fault1 pwrgd1 en1 en2 pwrgd2 fault2 status2 r h1 10 r hg1 47 c hg2 15nf r h2 10 r hg2 47 r5 100k r6 100k v sense1 + r7 100k r8 100k r9 100k v sense2 + r10 100k r1 20k r3 20k 12v 7.6a c l1 1600f + c l2 1600f + tmr1 tmr2
ltc4228-1/ltc4228-2 11 422812f a pplica t ions i n f or m a t ion monitors the load current for overcurrent detection. the hgate capacitor, c hg , controls the gate slew rate to limit the inrush current. resistor r hg with c hg compensates the current control loop, while r h prevents high frequency oscillations in the hot swap mosfet. during a normal power-up, the ideal diode mosfet turns on frst. as soon as the internally generated supply, intv cc , rises above its 2.2v undervoltage lockout threshold, the internal charge pump is allowed to charge up the cpo pins. because the hot swap mosfet is turned off at power-up, out remains low. as a result, the ideal diode gate drive amplifer senses a large forward drop between the in and out pins, causing it to pull up dgate to the cpo pin voltage. before the hot swap mosfet can be turned on, en must remain low and on must remain high for a 100ms debounce cycle to ensure that any contact bounces during the inser - tion have ceased. at the end of the debounce cycle, the internal fault latches are cleared. the hot swap mosfet is then allowed to turn on by charging up hgate with a 10a current source from the charge pump. the voltage at the hgate pin rises with a slope equal to 10a/c hg and the supply inrush current fowing into the load capacitor, c l , is limited to: i inrush = c l c hg ? 10a the out voltage follows the hgate voltage when the hot swap mosfet turns on. if the voltage across the current sense resistor, r s , becomes too high, the inrush current will be limited by the internal current limiting circuitry. once the mosfet gate overdrive exceeds 4.2v, the corresponding pwrgd pin pulls low to indicate that the power is good. once out reaches the input supply voltage, hgate continues to ramp up. an internal 12v clamp limits the hgate voltage above out. when both of the mosfets are turned on, the gate drive amplifer controls the gate of the ideal diode mosfet, to servo its forward voltage drop across r s , m d and m h to 25mv. if the load current causes more than 25mv of drop, the mosfet gate is driven fully on and the voltage drop across the mosfet is equal to i load t3 ds(on) . turn-off sequence the external mosfets can be turned off by a variety of conditions. a normal turn-off for the hot swap mosfet is initiated by pulling the on pin below its 1.155v threshold (80mv on pin hysteresis), or pulling the en pin above its 1.235v threshold. additionally, an overcurrent fault of suffcient duration to trip the circuit breaker also turns off the hot swap mosfet. normally, the ltc4228 turns off the mosfet by pulling the hgate pin to ground with a 300a current sink. all of the mosfets turn off when intv cc falls below its undervoltage lockout threshold (2.2v). the dgate pin is pulled down with a 100a current to one diode voltage below the in pin, while the hgate pin is pulled down to the out pin by a 200ma current. the gate drive amplifer controls the ideal diode mosfet to prevent reverse current when the input supply falls below out. if the input supply collapses quickly, the gate drive amplifer turns off the ideal diode mosfet with a fast pull-down circuit as soon as it detects that in is 20mv figure 2. ideal diode controller start-up waveforms figure 3. hot swap controller power-up sequence in 10v/div cpo 10v/div dgate 10v/div out 10v/div 20ms/div 422812 f02 on 5v/div hgate 10v/div out 10v/div pwrgd 10v/div 50ms/div 422812 f03
ltc4228-1/ltc4228-2 12 422812f below out. if the input supply falls at a more modest rate, the gate drive amplifer controls the mosfet to maintain out at 25mv below in. board presence detect with en if on is high when the en pin goes low, indicating a board presence, the ltc4228 initiates a 100ms timing cycle for contact debounce. upon board insertion, any bounces on the en pin restart the timing cycle. when the 100ms timing cycle is done, the internal fault latches are cleared. if the en pin remains low at the end of the timing cycle, hgate is charged up with a 10a current source to turn on the hot swap mosfet. if the en pin goes high, indicating a board removal, the hgate pin is pulled low with a 300a current sink after a 20s delay, turning off the hot swap mosfet without clearing any latched faults. overcurrent fault the ltc4228 features an adjustable current limit with circuit breaker function that protects the external mosfets against short circuits or excessive load current. the voltage across the external sense resistor (r s1 , r s2 ) is monitored by an electronic circuit breaker (ecb) and active current limit (acl) amplifer. the electronic circuit breaker will turn off the hot swap mosfet with a 300a current from hgate to gnd if the voltage across the sense resistor exceeds ?v sense(cb) (50mv) for longer than the fault flter delay confgured at the tmr pin. active current limiting begins when the sense voltage exceeds the acl threshold ?v sense(acl) (65mv), which is 1.3 the ecb threshold ?v sense(cb) . the gate of the hot swap mosfet is brought under control by the acl amplifer and the output current is regulated to maintain the acl threshold across the sense resistor. at this point, the fault flter starts the timeout with a 100a current charging the tmr pin capacitor. if the tmr pin voltage exceeds its threshold (1.235v), the external mosfet turns off with hgate pulled to ground by 300a, and its associated fault pulls low. after the hot swap mosfet turns off, the tmr pin ca - pacitor is discharged with a 2a pull-down current until its threshold reaches 0.2v. this is followed by a cool-off period of 14 timing cycles at the tmr pin. for the latch-off part (ltc4228-1), the hgate pin voltage does not restart at the end of the cool-off period, unless the latched fault is cleared by pulling the on pin low or toggling the en pin from high to low. for the auto-retry part (ltc4228-2), the latched fault is cleared automatically at the end of the cool-off period, and the hgate pin restarts charging up to turn on the mosfet. figure 4 shows an overcurrent fault on the 12v output. a pplica t ions i n f or m a t ion figure 4. overcurrent fault on 12v output figure 5. severe short-circuit on 12v output in the event of a severe short-circuit fault on the 12v output as shown in figure 5, the output current can surge to tens of amperes. the ltc4228 responds within 1s to bring the current under control by pulling the hgate to out voltage down to zero volts. almost immediately, the gate of the hot swap mosfet recovers rapidly due to the r hg and c hg network, and current is actively limited until the electronic circuit breaker times out. due to parasitic sup - ply lead inductance, an input supply without any bypass capacitor may collapse during the high current surge and then spike upwards when the current is interrupted. figure?11 shows the input supply transient suppressors consisting of z1, r snub1 , c snub1 and z2, r snub2 , c snub2 for the two supplies if there is no input capacitance. out 10v/div hgate 10v/div i load 40a/div 2s/div 422812 f05 out 10v/div hgate 10v/div i load 40a/div 100s/div 422812 f04
ltc4228-1/ltc4228-2 13 422812f active current loop stability the active current loop on the hgate pin is compensated by the parasitic gate capacitance of the external n-channel mosfet. no further compensation components are nor - mally required. in the case when a mosfet with c iss 2nf is chosen, an r hg and c hg compensation network connected at the hgate pin may be required. the value of c hg is selected based on the inrush current allowed for the output load capacitance. the resistor, r hg , connected in series with c hg accelerates the mosfet gate recovery for active current limiting after a fast gate pull-down due to an output short. the value of c hg should be 100nf and r hg should be between 10 and 100 for optimum performance. tmr pin functions an external capacitor, c t , connected from the tmr pin to gnd serves as fault fltering when the supply output is in active current limit. when the voltage across the sense resistor exceeds the circuit breaker trip threshold (50mv), tmr pulls up with 100a. otherwise, it pulls down with 2a. the fault flter times out when the 1.235v tmr threshold is exceeded, causing the corresponding fault pin to pull low. the fault flter delay or circuit breaker time delay is: t cb = c t ? 12[ms/f] after the circuit breaker timeout, the tmr pin capacitor pulls down with 2a from the 1.235v tmr threshold until it reaches 0.2v. then, it completes 14 cooling cycles consisting of the tmr pin capacitor charging to 1.235v with a 100a current and discharging to 0.2v with a 2a current. at that point, the hgate pin voltage is allowed to start up if the fault has been cleared as described in the resetting faults section. when the latched fault is cleared during the cool-off period, the corresponding fault pin pulls high. the total cool-off time for the mosfet after an overcurrent fault is: t cool = c t ? 11[s/f] if the latched fault is not cleared after the cool-off period, the cooling cycles continue until the fault is cleared. after the cool-off period, the hgate pin is only allowed to pull up if the fault has been cleared for the latch-off part (ltc4228 - 1). for the auto-retr y part (ltc4228-2), the latched fault is cleared automatically following the cool-off period and the hgate pin voltage is allowed to restart. resetting faults (ltc4228-1) for the latch-off part (ltc4228-1), an overcurrent fault is latched after tripping the circuit breaker, and the cor - responding fault pin is asserted low. if the ltc4228 controls the mosfets on two supplies, only the hot swap mosfet on the supply at fault is turned off and the other is not affected. to reset a latched fault and restart the output, pull the corresponding on pin below 0.6v for more than 100s and then high above 1.235v. the fault latches reset and the fault pin deasserts on the falling edge of the on pin. when on goes high again, a 100ms debounce cycle is initiated before the hgate pin voltage restarts. toggling the en pin high and then low again also resets a fault, but the fault pin pulls high at the end of the 100ms debounce cycle before the hgate pin voltage starts up. bringing all the supplies below the intv cc undervoltage lockout threshold (2.2v) shuts off all the mosfets and resets all the fault latches. a 100ms debounce cycle is initiated before a normal start-up when any of the supplies is restored above the intv cc uvlo threshold. auto-retry after a fault (ltc4228-2) for the auto-retry part (ltc4228-2), the latched fault is reset automatically after a cool-off timing cycle as described in the tmr pin functions section. at the end of the cool-off period, the fault latch is cleared and fault pulls high. the hgate pin voltage is allowed to start up and turn on the hot swap mosfet. if the output short persists, the supply powers up into a short with active current limiting until the circuit breaker times out and fault again pulls low. a new cool-off cycle begins with tmr ramping down with a 2a current. the whole process repeats itself until the output short is removed. since t cb and t cool are a func- tion of tmr capacitance, c t , the auto-retry duty cycle is equal to 0.1%, irrespective of c t . figure 6 shows an auto-retry sequence after an overcur - rent fault. a pplica t ions i n f or m a t ion
ltc4228-1/ltc4228-2 14 422812f tmr 1v/div hgate 5v/div fault 10v/div i load 20a/div 50ms/div 422812 f06 supply undervoltage monitor the on pin functions as a turn-on control and an input sup- ply monitor. a resistive divider connected between the input supply (in1 or sense1 + , in2 or sense2 + ) and gnd at the re - spective on pin monitors the supply undervoltage condition. the undervoltage threshold is set by proper selection of the resistors and is given by: v in(uvth) = 1 + r top r bottom ? ? ? ? ? ? ? v on(th) where v on(th) is the on rising threshold (1.235v). an undervoltage fault occurs if the input supply falls below its undervoltage threshold for longer than 20s. the fault pin will not be pulled low. if the on pin voltage falls below 1.155v but remains above 0.6v, the hot swap mosfet is turned off by a 300a pull-down from hgate to ground. the hot swap mosfet turns back on instantly without the 100ms debounce cycle when the input supply rises above its undervoltage threshold. however, if the on pin voltage drops below 0.6v, it turns off the hot swap mosfet and clears the associated fault latches. the hot swap mosfet turns back on only after a 100ms debounce cycle when the input supply is restored above its undervoltage threshold. an undervoltage fault on one supply does not affect the operation of the other sup - ply. the ideal diode function controlled by the ideal diode mosfet is unaffected by undervoltage fault conditions. if both in supplies fall until the internally generated sup- ply, intv cc , drops below its 2.2v uvlo threshold, all the mosfets are turned off and the fault latches are cleared. operation resumes from a fresh start-up cycle when the input supplies are restored and intv cc exceeds its uvlo threshold. there is a 10s glitch flter on the on pin to reject supply glitches. by placing a flter capacitor, c f , with the resis- tive divider at the on pin, the glitch flter delay is further extended by the rc time constant to prevent any false fault. power good monitor internal circuitry monitors the mosfet gate overdrive between the hgate and out pins. the power good status for each supply is reported via its respective open-drain output, pwrgd1 or pwrgd2. they are normally pulled high by an external pull-up resistor or the internal 10a pull-up. the power good output asserts low when the gate overdrive exceeds 4.2v during the hgate start-up. once asserted low, the power good status is latched and can only be cleared by pulling the on pin low, toggling the en pin from low to high, or intv cc entering undervoltage lockout. the power good output continues to pull low while hgate is regulating in active current limit, but pulls high when the circuit breaker times out and pulls the hgate pin low. cpo and dgate start-up the cpo and dgate pin voltages are initially pulled up to a diode below the in pin when frst powered up. cpo starts ramping up 7s after intv cc clears its undervolt - age lockout level. another 40s later, dgate also starts ramping up with cpo. the cpo ramp rate is determined by the cpo pull-up current into the combined cpo and dgate pin capacitances. an internal clamp limits the cpo pin voltage to 12v above the in pin, while the fnal dgate pin voltage is determined by the gate drive amplifer. an internal 12v clamp limits the dgate pin voltage above in. mosfet selection the ltc4228 drives n-channel mosfets to conduct the load current. the important features of the mosfets are on-resistance, r ds(on) , the maximum drain-source volt - age, bv dss , and the threshold voltage. the gate drive for the ideal diode mosfet and hot swap mosfet is guaranteed to be greater than 5v and 4.8v respectively when the supply voltages at in1 and in2 are between 2.9v and 7v. when the supply voltages at in1 and a pplica t ions i n f or m a t ion figure 6. auto-retry sequence after a fault
ltc4228-1/ltc4228-2 15 422812f in2 are greater than 7v, the gate drive is guaranteed to be greater than 10v. the gate drive is limited to not more than 14v. this allows the use of logic-level threshold n-channel mosfets and standard n-channel mosfets above 7v. an external zener diode can be used to clamp the potential from the mosfets gate to source if the rated breakdown voltage is less than 14v. the maximum allowable drain-source voltage, bv dss , must be higher than the supply voltages as the full sup- ply voltage can appear across the mosfet. if an input or output is connected to ground, the full supply voltage will appear across the mosfet. the r ds(on) should be small enough to conduct the maximum load current, and also stay within the mosfet s power rating. cpo capacitor selection the recommended value of the capacitor, c cp , between the cpo and in pins is approximately 10 the input capaci- tance, c iss , of the ideal diode mosfet. a larger capacitor takes a correspondingly longer time to charge up by the internal charge pump. a smaller capacitor suffers more voltage drop during a fast gate turn-on event as it shares charge with the mosfet gate capacitance. supply transient protection when the capacitances at the input and output are very small, rapid changes in current during input or output short- circuit events can cause transients that exceed the 24v absolute maximum ratings of the in and out pins. to mini - mize such spikes, use wider traces or heavier trace plating to reduce the power trace inductance. also, bypass locally with a 10f electrolytic and 0.1f ceramic, or alternatively clamp the input with a transient voltage suppressor (z1, z2). a 10, 0.1f snubber damps the response and eliminates ringing (see figure 11). design example as a design example for selecting components, consider a 12v system with a 7.6a maximum load current for the two supplies (see figure 1). first, select the appropriate value of the current sense resistors (r s1 and r s2 ) for the 12v supply. calculate the sense resistor value based on the maximum load current i load(max) , the minimum circuit breaker trip cur - rent i trip(min) and the lower limit for the circuit breaker threshold ? v sense(cb)(min) . a load current margin given as a ratio of i trip(min) /i load(max) is provided for allowing backfeeding current to fow through the sense resistor momentarily, without false tripping the circuit breaker on the higher supply before the reverse turn-off is activated on the lower supply. assuming a load current margin of 1.5 , i trip(min) = 1.5 ? i load(max) = 1.5 ? 7.6a = 11.4a r s = ? v sense(cb)(min) i trip(min) = 47.5mv 11.4a = 4.16m ? choose a 4m sense resistor with a 1% tolerance. next, calculate the r ds(on) of the mosfet to achieve the desired forward drop at maximum load. assuming a forward drop, ?v fwd of 60mv across the two external mosfets: r ds(on,total) ? v fwd i load(max) = 60mv 7.6a = 7.9m ? the si7336adp offers a good choice with a maximum r ds(on) of 3m at v gs = 10v, thereby giving a total of 6m for two mosfets in the supply path. the input ca - pacitance, c iss , of the si7336adp is about 5600pf. slightly exceeding the 10 recommendation, a 0.1f capacitor is selected for c cp1 and c cp2 at the cpo pins. next, verify that the thermal ratings of the selected mos- fet, si7336adp, are not exceeded during power-up or an output short. assuming the mosfet dissipates power due to inrush current charging the load capacitor, c l , at power-up, the energy dissipated in the mosfet is the same as the energy stored in the load capacitor, and is given by: e cl = 1 2 s c l s v in 2 for c l = 1600f, the time it takes to charge up c l is calculated as: t charge = c l s v in i inrush = 1600f s 12v 1a = 19ms a pplica t ions i n f or m a t ion
ltc4228-1/ltc4228-2 16 422812f the inrush current is set to 1a by adding capacitance, c hg , at the gate of the hot swap mosfet. c hg = c l ? i hgate(up) i inrush = 1600f ? 10a 1a = 16nf choose a practical value of 15nf for c hg . the average power dissipated in the mosfet is calculated as: p avg = e cl t charge = 1 2 ? 1600f ? 12v ( ) 2 19ms = 6w the mosfet selected must be able to tolerate 6w for 19ms during power-up. the soa curves of the si7336adp provide for 1.5a at 30v (45w) for 100ms. this is suff- cient to satisfy the requirement. the increase in junction temperature due to the power dissipated in the mosfet is ?t = p avg t;ui jc where zth jc is the junction-to-case thermal impedance. under this condition, the si7336adp data sheet indicates that the junction temperature will increase by 4.8c using zth jc = 0.8c/w (single pulse). the duration and magnitude of the power pulse during an output short is a function of the tmr capacitance, c t , and the ltc4228s active current limit. the short-circuit dura - tion is given as c t t ltc4228-1/ltc4228-2 17 422812f tca application in the tca application shown in figure 1, the output load capacitor is required to hold up the supply to the downstream load for a short duration when all of the in- put supplies are not available. this happens when the in supply collapses to ground momentarily while the other redundant supply to the diode-ored output is not turned on. as soon as the reverse voltage between in and out pins is detected, dgate is pulled down quickly to turn off the ideal diode mosfet. by placing the sense resistor in between the ideal diode and hot swap mosfet, it allows the sense + pin voltage to be held up by the output load capacitance temporarily when the input supply collapses. this prevents the sense + voltage from entering into un - dervoltage lockout and turning off the hot swap mosfet. as the in supply recovers, it charges up the depleted load capacitance and provides power to the downstream load instantly if the hot swap mosfet is not turned off. power prioritizer figure 8 shows an application where either of two supplies is passed to the output on the basis of priority, rather than simply allowing the highest voltage to prevail. the 5v pri- mary supply (input 1) is passed to the output whenever it is available; power is drawn from the 12v backup supply (input 2) only when the primary supply is unavailable. as long as input 1 is above the 4.3v uv threshold set by the r1-r2 divider at the on1 pin, m h1 is turned on connecting input 1 to the output. when m h1 is on, pwrgd1 goes low, which in turn pulls on2 low and disables the in2 path by turning m h2 off. if the primary supply fails and input?1 drops below 4.3v, on1 turns off m h1 and pwrgd1 figure 7. recommended pcb layout for power mosfets and sense resistors a pplica t ions i n f or m a t ion 28 27 26 25 24 23 9 1 2 3 4 5 6 7 8 22 21 20 19 18 17 16 15 10 11 12 13 14 ltc4228ufd c1 r h1 c cp1 r h2 z1 z2 vias to gnd plane r s1 in1 out1 out2 422812 f07 current flow to load ? ? ? ? ? ? ? m d1 powerpak so-8 m h1 powerpak so-8 s d s d s d g d m d2 powerpak so-8 m h2 powerpak so-8 s d s d s d g d d g d s d s d s d g d s d s d s ? ? ?? ? ?? ? r s2 current flow to load current flow to load current flow to load track width w: 0.03" per ampere on 1oz cu foil w in2 w w w c cp2
ltc4228-1/ltc4228-2 18 422812f a pplica t ions i n f or m a t ion goes high, allowing on2 to turn on m h2 and connect the input 2 to the output. diode d1 ensures that on2 remains above 0.6v while in the off state so that when on2 goes high, m h2 is turned on immediately without invoking the 100ms turn-on delay. when input 1 returns to a viable voltage, m h1 turns on and m h2 turns off. the ideal diode mosfets m d1 and m d2 prevent backfeeding of one input to the other under any condition. additional applications in most applications, the two external mosfets are con - fgured with the mosfet on the supply side as the ideal diode and the mosfet on the load side as the hot swap control. but for some applications, the arrangement of the mosfets for the ideal diode and the hot swap control may be reversed as shown in figure 9. the hot swap mosfet is placed on the supply side and the ideal diode mosfet on the load side with the source terminals connected to - gether. if this confguration is operated with 12v supplies, the gate-to-source breakdown voltage of the mosfets can be exceeded when the input or output is connected to ground as the ltc4228s internal 12v clamps only limit the dgate-to-in and hgate-to-out pin voltages. choose a mosfet whose gate-to-source breakdown voltage is rated for 25v or more as 24v voltage can appear across the gate and source pins of the mosfet during an input or output short. as shown in figure 9, if a mosfet with a lower rated gate-to-source breakdown voltage is chosen, an external zener diode clamp is required between the gate and source pins of the mosfet to prevent it from breaking down. figure 8. 2-channel power prioritizer cpo1 on1 en1 on2 en2 intv cc gnd c cp1 0.1f c1 0.1f c f1 0.1f c hg1 33nf c l 470f c t2 0.1f z1 smaj13a input 1 input 2 5v primary supply 12v backup supply c cp2 0.1f c t1 0.1f in1 sense1 ? sense1 + dgate1 m d1 sir466dp m h1 sir466dp ltc4228 r s1 0.006 m d2 sir466dp m h2 sir466dp r s2 0.006 r3 3.92k d1 ls4148 hgate1 r h1 10 r hg1 47 v out 5a out1 cpo2 in2 sense2 ? sense2 + dgate2 hgate2 out2 422812 f08 status1 fault1 pwrgd2 fault2 status2 z2 smaj13a r4 41.2k r2 49.9k r1 20k pwrgd1 tmr1 tmr2 + +
ltc4228-1/ltc4228-2 19 422812f a pplica t ions i n f or m a t ion figure 9. an application with the hot swap mosfet on the supply side and the ideal diode mosfet on the load side figure 10. plug-in card supply holdup using ideal diode at 12v and 3.3v input supplies cpo1 on1 v in1 12v pwren1 v in2 12v on2 intv cc gnd c1 0.1f c cp1 0.1f c cp2 0.1f c t2 47nf c hg1 15nf bulk supply bypass capacitor bulk supply bypass capacitor c t1 47nf 12v 5a plug-in card 1 plug-in card 2 backplane 422812 f09 sense1 + sense1 ? hgate1 m d1 sir466dp m h1 sir466dp ltc4228 r s1 0.006 m h2 sir466dp m d2 sir466dp z h1 , z d1 , z h2 , z d2 : cmhz4706 r s2 0.006 dgate1 out1 cpo2 in2 in1 sense2 ? sense2 + hgate2 dgate2 out2 status1 fault1 pwrgd1 en1 tmr1 tmr2 en2 pwrgd2 fault2 status2 r h1 10 z h1 z d1 r hg1 47 c hg2 15nf r h2 10 r hg2 47 12v 5a c l1 1000f pwren2 + c l2 1000f + z h2 z d2 cpo1 on1 en1 r2 137k r4 28k v in2 3.3v on2 en2 intv cc gnd c1 0.1f c f1 0.1f c f2 0.1f c cp1 0.1f z1 smaj13a c cp2 0.1f c t2 0.1f c l1 1000f 12v 10a c t1 22nf backplane connector card connector 422812 f10 ltc4228 m d2 sir468dp m h2 sir468dp r s2 0.015 cpo2 in2 sense2 ? sense2 + dgate2 hgate2 out2 status1 fault1 pwrgd1 tmr1 tmr2 pwrgd2 fault2 status2 c hg1 15nf in1 sense1 ? sense1 + dgate1 m d1 sir158dp m h1 sir158dp r s1 0.003 hgate1 out1 r h1 10 r hg1 47 r5 2.7k d1 d2 r6 2.7k v sense1 + r1 20k r3 20k z2 smaj13a v in1 12v d3 r7 2.7k r8 2.7k d1 d2 r9 2.7k v sense2 + d3 r10 2.7k + c l2 100f 3.3v 2a d1, d3: green led ln1351c d2: red led ln1261cal +
ltc4228-1/ltc4228-2 20 422812f figure 11. card resident application with the output diode-ored figure 12. battery application with the output diode-ored a pplica t ions i n f or m a t ion cpo1 on1 r2 88.7k r4 187k 15v power adapter supply 9v battery supply on2 en2 en1 intv cc gnd c1 0.1f c f1 10nf c f2 10nf c cp1 0.1f c cp2 0.1f c t2 47nf c hg1 15nf z1 smaj17a c t1 47nf 422812 f12 in1 sense1 ? sense1 + dgate1 m d1 sir466dp m h1 sir466dp ltc4228 r s1 0.006 m d2 sir466dp m h2 sir466dp r s2 0.006 hgate1 out1 cpo2 in2 sense2 ? sense2 + dgate2 hgate2 out2 status1 fault1 pwrgd1 pwrgd2 fault2 status2 r h1 10 r hg1 47 c hg2 15nf r h2 10 r hg2 47 r1 20k r3 20k v out 5a tmr1 tmr2 z2 smaj17a + c l 1000f + r2 137k r4 137k v in2 12v c f1 0.1f c f2 0.1f backplane connector card connector r1 20k r3 20k v in1 12v cpo1 on1 en1 on2 en2 intv cc gnd c1 0.1f c cp1 0.1f z1 smaj13a c cp2 0.1f c t2 47nf c l 1000f 12v 5a c t1 47nf 422812 f11 in1 sense1 ? sense1 + dgate1 m d1 sir466dp m h1 sir466dp ltc4228 r s1 0.006 m d2 sir466dp m h2 sir466dp r s2 0.006 hgate1 out1 cpo2 in2 sense2 ? sense2 + dgate2 hgate2 out2 status1 fault1 pwrgd1 tmr1 tmr2 pwrgd2 fault2 status2 r5 100k r6 100k v sense1 + z2 smaj13a r8 100k r9 100k v sense2 + r10 100k + c hg1 15nf r h1 10 r hg1 47 c hg2 15nf r h2 10 r hg2 47 c snub2 0.1f r snub2 10 c snub1 0.1f r snub1 10 r7 100k
ltc4228-1/ltc4228-2 21 422812f figure 13. 12v distribution in tca redundant power subsystem a pplica t ions i n f or m a t ion 12v 12v backplane power module #1 ? ? ? 16x (12 amcs, 2 cus, 2 mchs) in1 out1 sense1 ? sense1 + dgate1 ltc4228* hgate1 in2 out2 sense2 + sense2 ? dgate2 hgate2 in1 out1 sense1 ? sense1 + dgate1 ltc4228* hgate1 in2 out2 sense2 + sense2 ? dgate2 hgate2 in1 out1 sense1 ? sense1 + dgate1 ltc4228* hgate1 in2 out2 sense2 + sense2 ? dgate2 hgate2 in1 out1 sense1 ? sense1 + dgate1 ltc4228* hgate1 in2 out2 sense2 + sense2 ? dgate2 hgate2 amc #1 amc #2 12v 12v mch #1 mch #2 12v 12v power module #2 ? ? ? 8x ? ? ? 8x 12v 12v *additional details omitted for clarity 422812 f13
ltc4228-1/ltc4228-2 22 422812f ufd package 28-lead plastic qfn (4mm 5mm) (reference ltc dwg # 05-08-1712 rev b) p ackage descrip t ion please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. 4.00 0.10 (2 sides) 2.50 ref 5.00 0.10 (2 sides) note: 1. drawing proposed to be made a jedec package outline mo-220 variation (wxxx-x). 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (note 6) 0.40 0.10 27 28 1 2 bottom view?exposed pad 3.50 ref 0.75 0.05 r = 0.115 typ r = 0.05 typ pin 1 notch r = 0.20 or 0.35 45 chamfer 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (ufd28) qfn 0506 rev b recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 0.25 0.05 0.50 bsc 2.50 ref 3.50 ref 4.10 0.05 5.50 0.05 2.65 0.05 3.10 0.05 4.50 0.05 package outline 2.65 0.10 3.65 0.10 3.65 0.05
ltc4228-1/ltc4228-2 23 422812f information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. p ackage descrip t ion please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings. .386 ? .393* (9.804 ? 9.982) gn28 rev b 0212 1 2 3 4 5 6 7 8 9 10 11 12 .229 ? .244 (5.817 ? 6.198) .150 ? .157** (3.810 ? 3.988) 202122232425262728 19 18 17 13 14 16 15 .016 ? .050 (0.406 ? 1.270) .015 .004 (0.38 0.10) 45 0 ? 8 typ .0075 ? .0098 (0.19 ? 0.25) .0532 ? .0688 (1.35 ? 1.75) .008 ? .012 (0.203 ? 0.305) typ .004 ? .0098 (0.102 ? 0.249) .0250 (0.635) bsc .033 (0.838) ref .254 min recommended solder pad layout .150 ? .165 .0250 bsc .0165 .0015 .045 .005 * dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side ** dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side inches (millimeters) note: 1. controlling dimension: inches 2. dimensions are in 3. drawing not to scale 4. pin 1 can be bevel edge or a dimple gn package 28-lead plastic ssop (narrow .150 inch) (reference ltc dwg # 05-08-1641 rev b)
ltc4228-1/ltc4228-2 24 422812f linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com linear technology corporation 2012 lt 0812 ? printed in usa r ela t e d p ar t s typical a pplica t ion plug-in card diode-or application with hot swap first followed by ideal diode control part number description comments ltc1421 dual channel, hot swap controller operates from 3v to 12v, supports C12v, ssop-24 ltc1645 dual channel, hot swap controller operates from 3v to 12v, power sequencing, so-8 or so-14 ltc1647-1/ltc1647-2/ ltc1647-3 dual channel, hot swap controller operates from 2.7v to 16.5v, so-8 or ssop-16 ltc4210 single channel, hot swap controller operates from 2.7v to 16.5v, active current limiting, sot23-6 ltc4211 single channel, hot swap controller operates from 2.7v to 16.5v, multifunction current control, msop-8 or msop-10 ltc4215 single channel, hot swap controller operates from 2.9v to 15v, i 2 c compatible monitoring, ssop-16 or qfn-24 ltc4216 single channel, hot swap controller operates from 0v to 6v, active current limiting, msop-10 or dfn-12 ltc4218 single channel, hot swap controller operates from 2.9v to 26.5v, active current limiting, ssop-16 or dfn-16 LTC4221 dual channel, hot swap controller operates from 1v to 13.5v, multifunction current control, ssop-16 ltc4222 dual channel, hot swap controller operates from 2.9v to 29v, i 2 c compatible monitoring, ssop-36 or qfn-32 ltc4223 dual supply hot swap controller controls 12v and 3.3v, active current limiting, ssop-16 or dfn-16 ltc4224 dual channel, hot swap controller operates from 2.7v to 6v, active current limiting, msop-10 or dfn-10 ltc4225 dual ideal diode and hot swap controller operates from 2.9v to 18v, controls four n-channels, gn-24 or qfn-24 ltc4227 dual ideal diode and single hot swap controller operates from 2.9v to 18v, controls three n-channels, gn-16 or qfn-20 ltc4352 low voltage ideal diode controller operates from 0v to 18v, controls n-channel, msop-12 or dfn-12 ltc4354 negative voltage diode-or controller and monitor 80v operation, controls two n-channels, so-8 or dfn-8 ltc4355 positive high voltage ideal diode-or and monitor operates from 9v to 80v, controls two n-channels, s0-16 or dfn-14 ltc4357 positive high voltage ideal diode controller operates from 9v to 80v, controls n-channel, msop-8 or dfn-6 ltc4358 5a ideal diode operates from 9v to 26.5v, on-chip n-channel, tssop-16 or dfn-14 cpo1 on1 en1 v in2 5v on2 en2 intv cc gnd c1 0.1f c cp1 0.1f z1 smaj7a c cp2 0.1f c t2 0.1f c l 100f 5v 5a c t1 0.1f backplane connector card connector 422812 ta02 in1 sense1 ? sense1 + hgate1 m h1 si7790dp m d1 si7790dp ltc4228 r s1 0.006 m h2 si7790dp m d2 si7790dp r s2 0.006 dgate1 out1 cpo2 in2 sense2 ? sense2 + hgate2 dgate2 out2 status1 fault1 pwrgd1 tmr1 tmr2 pwrgd2 fault2 status2 z2 smaj7a v in1 5v pwren + r1 10k

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